Monday, December 20, 2004

"CHIPS: Analog decoders outdo digital in wireless test"
Advanced digital wireless standards like those overseen by the 3rd Generation Partnership Project use iterative communications protocols that provide error correction simultaneously with optimal compression. Until now, the most efficient way to correct errors in iterative codes has been to use rather power-hungry digital A/D converters and hardware multipliers to decode the wireless signals. But while digital decoders consume milliwatts of power, analog decoders use microwatts to achieve the lowest levels of noise interference and data corruption. Researchers at the University of Alberta have found a way to decode wireless signals using far less power than that consumed by digital A/D converters. "In one of our test chips, we have demonstrated that analog decoders can consume 100 times less power [40 picojoules of energy to decode one bit] while performing the same functions as a digital decoder. In another chip � with a block size of 256 � we showed that they could use up as little as a tenth of the area on the die," said University of Alberta EE David Nguyen.

Wednesday, December 08, 2004

"CHIPS: Groups move atomic lithography closer to fabs"
Two research groups in Holland have joined worldwide efforts to apply atomic lithography to nanoscale integration of semiconductors. Researchers using this method tackle the usual process in reverse: Instead of forcing light through a physical mask, they focus a physical beam of atoms with a mask made from standing waves of light. First demonstrated in 1997, atomic lithography has since been applied in labs in the United States, Japan and Europe for beams of matter as diverse as chromium, sodium and aluminum, as well as to indium and gallium. To that list, the Dutch researchers have added iron. "We have used iron, because we want to make magnetic nanostructures. Our substrate at the moment is simply a silicon wafer, but it is important to note that in principle any substrate material can be used � glass, metal, ceramic, even organic substrates," said Eindhoven University of Technology professor Ton van Leeuwen. Researchers in another Dutch group, led by professor Theo Rasing at Radboud University Nijmegen, report similar results.

Monday, December 06, 2004

"CHIPS: Unified transistor modeling on tap for IEDM"
A unified model for predicting the long-term reliability of semiconductors will be described next week at the 50th annual IEEE International Electron Devices Meeting. The technique, which simultaneously foretells negative-bias temperature instability and hot-carrier injection, could potentially save chip makers tens of millions of dollars annually. As nanoscale transistors shrink, the atomic-scale bonds that keep semiconductors reliable become fewer and fewer, making mean-time-to-failure predictions more important than ever. But to predict long-term reliability today, separate models must be maintained for the two primary causes of failure in semiconductors: negative-bias temperature instability (NBTI) and and hot-carrier injection (HCI). "Today, reliability is becoming much more important, because dimensions are getting so small," said Purdue University professor and semiconductor researcher Ashraf Alam, who will describe the details of a unified model at IEDM, to be held Dec. 13 to 15 in San Francisco ( "But only recently has reliability begun percolating into the design phase � rather than just being an afterthought. Our unified model will make it much easier for designers to measure reliability of new device architectures."