#MATERIALS: "ST Embraces Next-Gen Silicon-on-Insulator"

Silicon-on-insulator (SOI) wafers have a buried layer of insulating silicon-dioxide atop of which transistors are fabricated, adding to the cost of chips since SOI wafers are more expensive, but providing isolation from the substrate and nearby devices. However, it took the innovation of adding fully-depleted transistors (FD-SOI) to take the technology mainstream, since FD-SOI enables leakage currents that rival Intel's FinFETs, allowing chip makers to 'catch up with Intel." STMicroelectronics is the first major chip maker to commit to FD-SOI and in cooperation with SOI wafer provider Soitec has just offered its 28-nanometer FD-SOI process to European researchers: R. Colin Johnson

Here is what ST says about its FD-SOI process: STMicroelectronics (NYSE:STM), Soitec (Euronext) and CMP (Circuits Multi Projets) today announced that ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process, which uses innovative silicon substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. ST is releasing this process technology to third parties as it nears completion of its first commercial wafers.

The introduction in CMP’s catalogue of ST’s 28nm FD-SOI CMOS process builds on the successful collaboration that has allowed universities and design firms to access previous CMOS generations including 45nm (introduced in 2008), 65nm (introduced in 2006), 90nm (introduced in 2004), and 130nm (introduced in 2003). CMP’s clients also have access to 65nm and 130nm SOI (Silicon-On-Insulator), as well as 130nm SiGe processes from STMicroelectronics. For example, 170 universities and other companies have received the design rules and design kits for the ST 90nm CMOS process, and more than 200 universities and companies have received the design rules and design kits for the ST 65nm bulk and SOI CMOS processes.

Since CMP started offering the ST 28nm CMOS bulk technology in 2011, some 60 universities and microelectronics companies have received the design rules and design kits and 16 integrated circuits (ICs) have already been manufactured.

“There has been a great interest in designing ICs using these processes, with about 300 projects having been designed in 90nm (phased out in 2009), and more than 300 already in bulk 65nm,” said Bernard Courtois, Director of CMP. “In addition, more than 60 projects have already been designed in 65nm SOI and it is interesting to note that many top universities in Europe, USA/Canada and Asia have already taken advantage of the collaboration between CMP and ST.”

The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.

“With the first designs in FD-SOI technology already in the pipeline, the time is right to make the technology available to the research communities. Our FD-SOI manufacturing process allows existing designs to be quickly and easily ported to FD-SOI where significant power and performance benefit can be realized,” said Philippe Magarshack, Executive Vice President, Design Enablement and Services, STMicroelectronics. “In addition, ensuring that universities have access to our leading-edge technologies can help us attract the best young engineers as part of our commitment to remain a technology leader on a long-term basis.”

“Our partnership with STMicroelectronics and CMP is an additional example of Soitec’s commitment to providing differentiated materials solutions to the open market, supporting the continual expansion of the FD-SOI ecosystem and users of advanced technologies,” said Steve Longoria, senior vice president of worldwide strategic business development for Soitec. “Through this partnership we will see new and innovative products based on Soitec's FD-SOI materials, as a result of providing universities and other customers with a proven path for developing and testing next-generation integrated circuits.”
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