3-D chips from Stanford connect four layers with standard vias, with the bottom being standard CMOS, the top carbon-nanotube logic transistors, and the middle two layers of resistive random access memory (RRAM).
FULL STORY AT EE TIMES
Friday, December 19, 2014
#3-D: True 3-D chips build up layers rather than stack die"
True 3-D chips build layer upon layer in the fab rather than just stack die. These researchers through in low-temperature nanotube processing to sandwich two RRAM layers between to layers of logic, with more to come: R. Colin Johnson @NextGenLog and EE Times
3-D chips from Stanford connect four layers with standard vias, with the bottom being standard CMOS, the top carbon-nanotube logic transistors, and the middle two layers of resistive random access memory (RRAM).
FULL STORY AT EE TIMES
3-D chips from Stanford connect four layers with standard vias, with the bottom being standard CMOS, the top carbon-nanotube logic transistors, and the middle two layers of resistive random access memory (RRAM).
FULL STORY AT EE TIMES
