Check out all the details of thermal co-design at DesignCon 2013 session Thermal Co-analysis of 3D-IC/Packages/System on Tuesday, Jan. 29 at 11:05 am at the Santa Clara Convention Center.
Further Reading
Wednesday, January 16, 2013
#3D: "Co-Design Key to Success"
3D semiconductors have special problems with overheating, making thermal co-design a must-have for the chip designer. Learn how to co-design 3D chips for thermal stability at DesignCon 2013: R. Colin Johnson @NextGenLOg
Temperature aware 3D-IC designs (left) represent device-layer power on a map of tiles (middle) each of which has its own temperature-dependent leakage profile (right).
Check out all the details of thermal co-design at DesignCon 2013 session Thermal Co-analysis of 3D-IC/Packages/System on Tuesday, Jan. 29 at 11:05 am at the Santa Clara Convention Center.
Further Reading
Check out all the details of thermal co-design at DesignCon 2013 session Thermal Co-analysis of 3D-IC/Packages/System on Tuesday, Jan. 29 at 11:05 am at the Santa Clara Convention Center.
Further Reading
