"CHIPS: clock technique resonates for nixing jitter"

Details about a resonant clock distribution circuit jointly developed by IBM Corp. and Columbia University will be revealed at the IEEE's International Solid-State Circuits Conference next month. The second-generation design builds on last year's IBM-Columbia paper, but this time with a bottom-up approach that is one step away from possible commercialization. Last year, by canceling capacitive loading with integrated inductors, IBM and Columbia solved the jitter and skew problems of distributing gigahertz to terahertz clock signals in a prototype chip that retrofitted IBM's current clock distribution circuitry. This year, the IBM-Columbia design will feature a resonant oscillator solution that, if successful, will redefine the way clock distribution is done on high-end IBM processors. "I can't tell you the details of our new design before the ISSCC paper, except to say that we looked at everybody's resonant clocking techniques and have come up with a solution which we think will change the way clock signals are distributed on high-end processor chips," said Steven Chan, an EE at Columbia University. Chan works under EE and professor Ken Shepard in cooperation with physicist Phillip Restle at IBM's T.J. Watson Research Center (Yorktown Heights, N.Y.)
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