Monday, June 06, 2005

"CHIPS: Vision chips' mimic eye, brain functions"

As the long development of charge-coupled device (CCD) and CMOS active-pixel sensor technology begins to pay off in the form of affordable all-electronic still and video cameras, a second wave of solid-state imaging chips with very different capabilities is emerging from research labs around the world. Called "vision chips," these silicon imaging devices are typically parallel computers on a chip implementing a processor per pixel to mimic neural processing circuitry in the retina. Rather than striving for high resolution and faithful color reproduction, vision chips capture other aspects of the eye and brain functions, such as edge and motion detection. Target applications include security systems, autonomous robots, artificial implantable retinas and biochemical analysis. A few projects have reached the commercial stage, including a real-time in vivo glucose-monitoring system from Array Vision Engineering Co. (Alachua, Fla.) and a security camera being marketed by Pixim Inc. (Mountain View, Calif.), which has commercialized research from a project at Stanford University. An example of state-of-the-art vision chip technology surfaced at last month's International Symposium on Circuits and Systems in Kobe, Japan, where EE professor Piotr Dudek of the University of Manchester (England) demonstrated a third-generation device with 16,384 pixel-processors that mimics the retina. Called Scamp, for "SIMD current-mode analog-matrix processor," the chip integrates an arithmetic-logic unit, memory, control logic and an input/output circuit behind each and every pixel. The Scamp-3 vision chip promises to enable robots and automated inspection, surveillance and vehicle-guidance systems to "see" in a manner similar to human sight. The Scamp-3 is a 1-cm2 chip fabricated in 0.35-micron CMOS that arranges its 16,384 pixel-processors in a 128 x 128 array. Each pixel-processor measures 50 microns2 and consumes 12 microwatts when running at 1.25 MHz, giving the chip a computational power efficiency of 104 billion instructions per second per watt.