"CHIPS: Coating lets nanotube transistors self-assemble on chips"

Next-generation semiconductors aim to harness the ballistic electron transport capabilities of pure carbon nanotubes, but until now there has been no easy way to integrate the tubes with silicon chips. Now IBM Corp. researchers think they have the solution--coat nanotubes with a ligand that only sticks to high-k dielectrics, then lithographically pattern the wafer with high-k dielectrics wherever transistor channels are wanted. The researchers showed that carbon nanotubes would self-assemble on the lithographically defined channels and that annealling boiled off their ligand coating, leaving behind arrays of carbon nanotube transistors. Normally, when used as the channel for a transistor, carbon nanotubes are many times smaller than the source and drain electrodes--less than 1 nanometer, compared with tens or hundreds of nm. This makes it difficult to fabricate them using traditional lithographic techniques. The process runs on any standard CMOS semiconductor fabrication line. In their proof-of-concept demonstration chip, the IBM researchers fabricated an array of nanotube transistors by patterning 40-nm-deep x 300-nm-wide aluminum lines on a silicon dioxide wafer, placing them where transistor channels were supposed to be. The aluminum was then oxidized to turn it into a high-k dielectric. Next, the chemically treated nanotubes, in an ethanol solution, were applied to the wafer. At this point, the nanotubes stuck only to the high-k dielectric pattern and not to the silicon dioxide substrate. Finally, the IBM team patterned electrodes for the source and drains of the transistors. The resultant demonstration transistors had a 400-nm channel length.
Text: http://www.eetimes.com/showArticle.jhtml?articleID=186500363