Vias on printed-circuit boards are metal-clad holes that connect component leads on the top to component leads on the bottom. Similarly, on chips, semiconductor circuitry on one layer can be connected to a second layer via a hole, etched in the interlayer dielectric, which is then filled with metal. Now Purdue University engineers have demonstrated a semiconductor fabrication technique that uses tiny, 30- to 50-nanometer-pitch arrays of vertically grown carbon nanotubes for vias be- tween layers on semiconductor chips. The technique, devised by Timothy Fisher and Timothy Sands at Purdue's Birck Nanotechnology Center, works by virtue of "porous anodic alumina," which can form a network of evenly spaced pores in an aluminum oxide dielectric layer and then grow carbon nanotubes through the pores to form vias between layers. The technique produces both single- and double-walled carbon nanotubes. Each pore grows only a single tube, suggesting that the vias can be strictly controlled. That would make them easier to integrate with normal CMOS circuitry.