"MATERIALS: Gate leakage, down and out?"

A high-k dielectric process for CMOS transistors promises to turn the International Semiconductor Roadmap into a freeway by eliminating the gate-leakage problem at advanced nodes down to 10 nanometers. Overheating due to excessive gate leakage is the number one hurdle to reaching advanced semiconductor nodes below 45 nanometer. Now, a process with 1 million times less gate leakage could enable rapid migration to advanced nodes, according to Clemson University researchers.
Text: http://www.eetimes.com/showArticle.jhtml?articleID=204700285