Wednesday, March 18, 2009
Interconnecting bare die to form 3-D chip stacks is best done by low-temperature wafer bonding before dicing, according to Rensselaer Polytechnic Institute (RPI) researchers who described how to perform the process with nanoscale copper rods. Using a chemical vapor deposition technique, the researchers were able to demonstrate how "intermittent annealing" provided lower temperatures to melt the copper nano-rods, enabling safe bonding of wafers into a single stack that could then be diced into 3-D chips.
BOTTOM LINE: With the industry rushing toward 3D chip stacks, an increasing number of technques are being developed to bond wafers together before dicing them into chips. The reason is that aligning wafer handling tools are much more precise than chip handling tools, permitting smaller pads connecting layers through silicon vias. These researchers have found a way to harness nanotechnology to perform the wafer bonding at a very low temperature, which should bring 3D "cubes" of silicon to within reach in three to five years.
Posted by R. Colin Johnson at 3:29 PM