As chips approach the atomic scale in dimensions, the possibilities increase for cracks to develop during manufacturing, or for fractures to develop during use. To the rescue is a new method called peridynamic theory which can predict faults before they happen--giving engineers the chance to fix the weaknesses before fabricating the chips (check out the figure below where a predicted crack, top, was confirmed experimentally, bottom). Look for peridynamic theory to become a integral part of the test and verification suite used by design engineers for new chips over the next five years. R.C.J.
Engineers could detect design flaws resulting in cracks, fractures and interface faults before chip fabrication using a new method that harnesses an electronics failure simulation technique called peridynamic equations. Instead of the traditional differential equations and finite element methods used to model semiconductors, investigators from Semiconductor Research Corp. (SRC) and University of Arizona propose that manufacturers adopt peridynamic equations in order to spot faults involving discontinuities during the chip design stage.