![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDDQ5ShX7_2LwmM91GvxMaMyhRRhUuAqKzwgVujmor6vAOcfUT5CImYgW_tLFUr4UJug55NNmuI5BQ8K9vy35dNKKoho09xe_r8CkmKsn8NjXMXlq9YcdksnxnJxEXYVcbjZdaaQ/s640/rcj_Micron_Intel_Xeon+Phi_Supercomputer_1.jpg)
Micron's 2-gigabyte and 4-gigabyte parts will help customers increase channel bandwidth to 120 and 160 gigabytes per second, respectively. For Intel, Micron is customizing a 16-gigabyte part to supply channels optimized to the massively parallel processors on the next-generation Knights Landing Xeon Phi.
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7ngaw_EnV7LQuJUnawBoA2Owh5CaERtsduqHpKbfa3LQiZ9bJHw40YUMC3UmqKlnM2u7bDtAV-nvHRjEi8c7p8RoI0zlYDyO9Bu73h2-00z8ydiWTKd07kX7MPOfLejsoM-I4pA/s640/rcj_Micron_Intel_Xeon+Phi_Supercomputer_2.jpg)
Micron has been working with Intel for several years to optimize the interface channels to maximize bandwidth to its processors. At the 2011 Intel Developers Conference, it demonstrated a single interface channel with a bandwidth of more than 1 terabit per second (seven times greater than DDR3). It also claimed the lowest-ever energy consumption of approximately 8 picoJoules per bit.
Further Reading