"CHIPS: Analog decoders outdo digital in wireless test"
Advanced digital wireless standards like those overseen by the 3rd Generation Partnership Project use iterative communications protocols that provide error correction simultaneously with optimal compression. Until now, the most efficient way to correct errors in iterative codes has been to use rather power-hungry digital A/D converters and hardware multipliers to decode the wireless signals. But while digital decoders consume milliwatts of power, analog decoders use microwatts to achieve the lowest levels of noise interference and data corruption. Researchers at the University of Alberta have found a way to decode wireless signals using far less power than that consumed by digital A/D converters. "In one of our test chips, we have demonstrated that analog decoders can consume 100 times less power [40 picojoules of energy to decode one bit] while performing the same functions as a digital decoder. In another chip � with a block size of 256 � we showed that they could use up as little as a tenth of the area on the die," said University of Alberta EE David Nguyen.