"CHIPS: Embedded superlattice slashes gate leakage"

CMOS devices isolate transistor gates from their channels with supposedly impenetrable oxides. But as chips scale below the 65-nanometer node, those oxides become so thin that applying enough voltage to turn on a transistor also enables a percentage of the electrons charging the gate to tunnel through the oxide into the channel. Mears Technologies addresses the leakage problem by adding an embedded superlattice during the construction of a transistor's channel to enhance current flow in the plane of the channel, while simultaneously blocking current flow perpendicular to the channel, thereby mitigating gate leakage. It claims its sili- con-on-silicon superlattice can reduce gate leakage by 70 to 90 percent, while increasing current drive in the channel.
Text: http://www.eetimes.com/showArticle.jhtml?articleID=196602004