The world's first 3-D chip process is ready for licensing from the fabless semiconductor design house BeSang Inc, which recently demonstrated chips with 128 million vertical transistors for memory bit cells above their control logic. The chips were designed at the National Nanofab Center (Daejeon, South Korea) and Stanford Nanofab (Palo Alto, Calif.). BeSang said its process, which is protected by over 25 patent applications, will allow flash, DRAM and SRAM to be placed atop logic, microprocessor cores and SoCs. BeSang claims it achieved 3-D by fabricating logic circuitry using a high-temperature process on the bottom and by fabricating memory circuitry using a low-temperature process on top of the logic. By placing logic and memory on different layers of the same 3-D chip, BeSang's process packs in more die per wafer, which translates into lower costs per die.
Text: http://www.eetimes.com/showArticle.jhtml?articleID=210001905
