Ziptronix (Research Triangle Park, N.C.) said the technology can be used for either wafer-to-wafer or chip-to-wafer stacking, further claiming that its 3-D bonding process is low-cost and provides high yields. The details were revealed in U.S. Patent 7,387,944 (on low temperature covalent bonding) and U.S. Patent 6,962,835 (on the direct bond interconnect). Based on through-silicon vias (TSVs), the company claims its low-temperature oxide bond provides a metal-to-metal contact for vias, without the high temperatures necessary when using thermal compression techniques.
Text: http://www.eetimes.com/showArticle.jhtml?articleID=211600160
