Thursday, February 26, 2009
3D chips promise to pack more punch compared to today's flat planar chips, usually by stacking dies and connecting them with through silicon vias. Massachusetts Institute of Technology professor George Barbastathis, on the other hand, recommends unfolding chip structures into the third dimension and has demonstrated that capacitors are amenable to the technique. He predicts that tiny motors and other devices will soon be fabricated using his nanoscale "origami" approach.
BOTTOM LINE: 3D chips solve many problems plaguing traditional planar semiconductors, such as packing logic above memory cells without the need for long costly interconnections. MEMS chips also harness the third dimension by sculpting out 3D structures with etching techniques. MIT's origami-like alternative is not really an alternative to 3D stacked dies, but the technique is so novel that I suggest keeping an eye on its development, which could take a decade or more to mature.
Posted by R. Colin Johnson at 4:02 PM