Wednesday, April 08, 2009
Atomically thin layers of pure carbon atoms in a perfect crystalline lattice--graphene--have vastly greater electron mobility than silicon or gallium arsenide. Unfortunately, graphene is very difficult to grow in uniform sheets. To the rescue is a Ohio State University method, currently being patented, which has the advantage of enabling cheap available bulk crystals of graphite to be patterned into intricate graphene circuitry which can be placed atop a conventional silicon chip. A reusable graphene template patterns all of a chip's carbon-transistor circuitry using in a single micro-contact stamping operation.
"Basically the idea is to stamp layers of graphene in arbitrary shapes on silicon substrates," said Ohio State professor Nitin Padture. " Stamps can be patterned for large areas with dots, squares, lines, whatever shape you need--and can be used over and over, making it a good candidate for production environments."
To prove the concept, Padture's group used conventional photolithography techniques to pattern graphene stamps made from highly-oriented pyrolytic graphite bulk crystals. Each stamp measured three-by-three millimeter square and used about a one millimeter thickness of layered graphene. Since each use of the stamp only deposits a few layers of graphene--some less than a four nanometers thick--it could be reused to stamp out the same graphene circuitry atop millions of silicon chips.
For their tests, the researchers stamped square shapes onto a 300 nanometer layer of insulating silicon dioxide atop a conventional silicon wafer. Because of the strong van der Waal force between graphene and silicon dioxide, the graphite stamp deposited just a few monolayers to the wafer with each application.
Padture's group hopes to gain control of how many layers graphene get deposited with each stamping--eventually permitting consistent deposition of atomically thin monolayers--by adjusting the force of adhesion to the graphite block with custom material mixes for the subtrate.
Using a stamp in the shape of a field of square pillars--each about five microns square--Padture's group was able to depost an array of graphene channels which they are currently characterizing for their electrical characteristics when used for field-effect transistors (FETs).
"We are attaching electrodes to each corner of the graphene squares and are just beginning to test them," said Padture. "Our circuit will demonstrate using the material to make FETs."
Padture, who is also director of Ohio State's Center for Emergent Materials, performed the work with professor Wolfgang Windl and postdoctoral researcher Dongsheng Li. Funding was provided by the Ohio State's Institute for Materials Research as well as by the National Science Foundation (NSF) sponsored Center for Emergent Materials--one of 27 NSF-sponsored Materials Research Science & Engineering Centers (MRSECs) nationwide.
Posted by R. Colin Johnson at 8:47 AM