#MICROCHIP "Low-k test regime spots defects on wafers" #Semiconductor

Columbia's noninvasive trap-counting technique makes low-k dielectrics less of a dice roll. Look for a new generation of low-k dielectric materials that act as super-insulators on future chips.


Low-k dielectric materials are super-insulators that help designers scale down chip size, but at the expense of shortening the average lifetimes of their chips. The problem is that low-k dielectrics add porosity—vacancy defects—which can act as electron traps, letting current leak through the insulator and eventually short-circuiting the chip. Now, by using photo-induced current and laser-based second-harmonic generation, researchers at Columbia University are perfecting a testing regime for Semiconductor Research Corp. (SRC; Durham, N.C.) that can spot potential failures while the chips are still on the wafer.
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