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| Conventional clock generators (left) use a separate power hungry phase-locked loop (PLL) for each frequency, but Silicon Lab's Multisynth used a single PLL with fractional multipliers to cut power, cost and size. |
Analog and mixed-signal chip maker Silicon Laboratories Inc. introduced a clock generator that synthesizes any eight frequencies—without the need for separate phased-locked loops (PLLs)—Tuesday (Nov. 9) at Electronica 2010 in Munich, Germany. Silicon Labs' Multisynth technology nixes separate PLLs in favor of fractional frequency multipliers that cut power, lower jitter and shrink the size of traditional clock generators, according to company executives.
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