Many startups have crafted massive multi-core processors as a solution to the inability to crank chip clock speeds much past 3GHz due to overheating problems, such as Tilera which has a 64-core processor that uses a proprietary instruction set. Also graphics coprocessor makers, notably Nvidia, are putting hundreds of tiny cores on their graphics-processing-units (GPUs) but which also use a proprietary instruction set. The difference with Intel's Xeon Phi is that the cores are all x86 compatible, allowing the same multiprocessing software development already in place to harness a massively parallel processor. Intel is packing every trick it knows about accelerating parallel processing into its many integrated core (MIC) architecture for the Xeon Phi, but all use technologies already proven out in Intel's existing processor families, making Intel's solution a single-chip-supercomputer that can be harnessed by any server or workstation already using Xeons: R. Colin Johnson
The Knights Ferry MIC architecture board housed this 32-core Aubrey Isle processor, the forerunner of the 50-core Xeon Phi, to be available on Knights Corner boards this fall. Source: Intel
Here is what Go-Parallel says bout Intel's Xeon Phi: Intel’s Xeon Phi – its first commercial Many Integrated Core (MIC) processor officially due out this fall – promises to bring massive multiprocessors down from the lofty heights of world-class supercomputers to the domain of enterprise servers and workstations. By installing 50-core Xeon Phi processors on Knight’s Corner PCIe 3.0 boards, any Xeon-based server or workstation will be able to access the teraFLOPS performance levels previously only available to government labs and well-endowed corporate researchers.
If we look inside the Xeon Phi, however, we do not find exotic, untested technologies like those that have drained the R&D budgets of rival multiprocessor startups, but leading-edge semiconductor processes and architectural features that already have been proven out by existing Intel multi-core processors. Intel’s latest 22-nanometer CMOS process – the Ivy Bridge die shrink of its proven Sandy Bridge microarchitecture – uses its pioneering 3-D FinFET transistors that already have put Intel years ahead of its semiconductor rivals worldwide. But just as important to the Xeon Phi’s performance is its use of the high-speed ring architecture, which had already been perfected for Intel’s second-generation Core processors and serves as the backbone of its latest multi-core Xeon processors...