Tuesday, July 24, 2012

#CHIPS: "Virtualized Symmetric Multiprocessing Eases MIC Transition"

Intel's 50+ core Xeon Phi will bring massive parallelism to the x86 platform, but requires an "off-load" programming model since the extra cores will be on a PCIe card. However, ScaleMP is working with Intel to ease that transition by virtualizing those cores with its vSMP. The extra bonus is that any missing instructions on the Xeon Phi will be emulated as well, so that code already written for any Xeon should run unaltered on the 50+ core Xeon Phi coprocessor: R. Colin Johnson

ScaleMP virtualizes dual Xeon E5-2600 processors with 128 Gbytes and a 50-core Xeon Phi coprocessor board with 8 Gbytes of memory, making it appear to programmers as a virtual SMP with a 66-core Xeon processor and 136 Gbytes of memory. Source: ScaleMP

Here is what Go-Parallel says about virtualized Xeon Phi cores: Programming multicore processors like the Xeon E5 for optimal performance isn’t easy, but because of the shared memory model, and hardware support for cache coherence, a little effort can go a long way toward harnessing multiple processors to accelerate applications. And with the help of the growing library of OpenMP algorithms that have already been optimized for multi-core acceleration, programmers are starting to see light at the end of multi-processing tunnel. At first glance, however, the new Intel Many Integrated Core (MIC) architecture for the forthcoming massively parallel Xeon Phi family would require a different style of programming. The exact same techniques cannot be used with the 50-core Xeon Phi, because it locates those extra cores on a PCIe coprocessor card. The Xeon E5 host processor shares its memory among eight on-chip cores, but not among the Xeon Phi cores, which have their own memory space. Programmers can just use the host Xeon E5 just for housekeeping, and load their parallelized algorithms into the Xeon Phi, but then their parallel algorithms are restricted to the memory available on the coprocessor card. Fortunately, there is a solution that lets programmers ease into the MIC architecture, and Intel is working with ScaleMP Inc. (Cupertino, Calif.) to make this transition (nearly) painless.
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