Here is what the Symposia is saying about their learning courses and moderated discussions: The 2012 Symposia on VLSI Technology and Circuits have announced further details of the Short Courses and first-ever Joint Focus Sessions to be held at this year’s edition of these annual meetings, which are the premier mid-year gatherings for the presentation of cutting-edge research in microelectronics technology and circuit development. The Symposia will be held at the Hilton Hawaiian Village hotel here from June 12-14 (Technology) and from June 13-15 (Circuits). The Symposia alternate between Hawaii and Japan annually.
This year’s Symposia include 55 sessions with more than 200 presentations, as well as keynote speeches, evening panel discussions, a luncheon talk, and evening reception and banquet. The Symposia will be preceded by Short Courses and the Silicon Nanoelectronics Workshop.
Short Courses
-- VLSI Technology Short Course (June 11) -- “14nm CMOS Technology & Design Co-Optimization and Emerging Memory Technologies” -- This course will comprise six lectures given by distinguished speakers, covering state-of-the-art technology and circuit design for 14nm-generation CMOS. It will start with a perspective on the history and future of FinFET technology by Prof. Tsu-Jae King Liu of UC-Berkeley where FinFETs were first developed, followed by discussion on design enablement for FinFET technology from a foundry perspective by Dr. Sheu of TSMC. Prof. Takagi from the University of Tokyo will cover the state-of-the-art in high-mobility channel devices and their integration onto silicon substrates. Technical challenges and potential process/design solutions for patterning and interconnects will be presented by Dr. Levinson from GLOBALFOUNDRIES and Dr. Angyal of IBM Corporation, respectively. Finally, Dr. Koh of Samsung will describe emerging memory technologies and contrast their prospects and requirements.
-- VLSI Circuits Short Courses (June 12) -- Two parallel full-day courses will be given by 12 distinguished international speakers from industry and academia. A single registration fee covers both, and participants can switch between the two. Afterward, a roundtable for both Circuits courses will be held to foster interaction and discussion with all speakers.
- “Designing in Advanced CMOS Technologies” will focus on the challenges sub-32nm technology nodes pose to VLSI designers. It will start with two process-oriented presentations by Tsu-Jae King Liu of UC-Berkeley and Thomas Skotnicki of STMicroelectronics, discussing evolutionary and disruptive scaling solutions, covering bulk CMOS devices, FinFETs and SOI devices. Next, challenges and future concepts of SRAM scaling for large embedded-memory applications will be presented by Fatih Hamzaoglu of Intel. Then, mixed-signal and power-aware design challenges will be discussed by Fu-Lung Hsueh of TSMC and Youngsoo Shin of KAIST, respectively, taking into account layout effects as well as a transistor’s analog behavior. These will be followed by a discussion on advanced CAD flows addressing custom design challenges in new technology nodes, by David White of Cadence.
- The second Circuits Short Course, “Ultra Low Power SoC Design for Future Mobile Systems,” will cover the technical requirements needed to successfully realize next-generation mobile systems. Speakers will cover digital circuit techniques for logic and memory, as well as system-level aspects. The course will start with a broad vision of the future of mobile systems by Jan Rabaey of UC-Berkeley, and then four talks by Masaya Sumita of Panasonic, Kyomin Sohn of Samsung, Gangadhar Burra of Texas Instruments and Jared Zerbe of Rambus will focus on the most important aspects of design optimization, including logic design, memory systems, RF/analog and architecture-optimization, as well as high-performance, low-power signaling, respectively. A complete case study on a multi-core cellular platform with a specific focus on system-level aspects by John Redmond of Broadcom will end the course.
New VLSI Symposia Technology/Circuits Joint Focus Sessions
The new Technology/Circuits Joint Focus Sessions are devoted to advanced device and circuit design co-optimization, a key ingredient for future progress. They are:
-- Memory (Wednesday morning, June 13), featuring:
- SRAMs Design in Nano-Scale CMOS Technologies (Invited), K. Zhang, Intel Corp.
- Hybrid Memory Cube New DRAM Architecture Increases Density and Performance (Invited), J. Jeddeloh et al. Micron
- Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies (Invited), T. Endoh et al., Tohoku University
- A Highly Pitch Scalable 3D Vertical Gate (VG) NAND Flash Decoded by a Novel Self-Aligned Independently Controlled Double Gate (IDG) String Select Transistor (SSL), C.-P. Chen et al., Macronix International, Ltd.
-- 3-D System Integration (Wednesday afternoon), featuring:
- Practical Implications of Via-Middle Cu TSV-induced Stress in a 28nm CMOS Technology for Wide-IO Logic-Memory Interconnect (Invited), J. West et al.,Texas Instruments, Inc.
- Thermal Stress Characteristics and Impact on Device Keep-Out Zone for 3-D ICs Containing Through-Silicon-Vias (Invited),T. Jiang et al., University of Texas-Austin and Hynix
- Near-Field Wireless Connection for 3D-System Integration (Invited), T. Kuroda, Keio University
- An Ultra-Thin Interposer Utilizing 3D TSV Technology, W.-C. Chiou et al., TSMC
-- Emerging Non-Volatile Memory (Wednesday afternoon), featuring:
- A 0.13µm 8Mb Logic Based CuxSiyO Resistive Memory with Self-Adaptive Yield Enhancement and Operation Power Reduction, X.Y. Xue et al., Fudan University and Semiconductor Manufacturing International Corp.
- A 3.14 um2 4T-2MTJ-Cell Fully Parallel TCAM Based on Nonvolatile Logic-in-Memory Architecture, S. Matsunaga et al., Tohoku University and NEC Corp.
- 1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique with 1.0ns/200ps Wake-up/Power-off Times, T. Ohsawa et al., Tohoku University and NEC Corp.
- A Simple New Write Scheme for Low Latency Operation of Phase Change Memory, Y.-Y. Lin et al, Macronix International Co., Ltd. and IBM Corp.
- Analysis of Random Telegraph Noise and Low Frequency Noise Properties in 3-D Stacked NAND Flash Memory with Tube-Type Poly-Si Channel Structure, M.-K. Jeong et al., Seoul National University and Hynix Semiconductor Inc.
-- Advanced SRAM (Thursday morning, June 14), featuring:
- A 0.41µA Standby Leakage 32Kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28nm HKMG CMOS, N. Maeda et al., Renesas Electronics Corp.
- A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges, S. Moriwaki et al., Semiconductor Technology Academic Research Center, Panasonic Corp. and University of Tokyo
- A SRAM Cell Array with Adaptive Leakage Reduction Scheme for Data Retention in 28nm High-K Metal-Gate CMOS, P. Hsu et al., TSMC
- A 28nm High-k Metal-Gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) Circuitry Achieving 3X Reduction on Speed Variation for Single Ended Arrays, R. Lee et al., TSMC
-- Design in Scaled Technologies (Thursday morning), featuring:
- Design Enablement at 14nm: The Challenge of Being Early, Accurate, and Complete (Invited), M.E. Mason, Texas Instruments Inc.
- Designing in Scaled Technologies: 32nm and Beyond (Invited), S. Kosonocky et al., AMD Inc.
- The Optimum Device Parameters for High RF and Analog/MS Performance in Planar MOSFET and FinFET (Invited) T. Ohguro et al., Toshiba Corp.
- Dynamic Intrinsic Chip ID Using 32nm High-K/Metal Gate SOI Embedded DRAM, D. Fainstein et al., IBM Corp.
- A Fully-Digital Phase-Locked Low Dropout Regulator in 32nm CMOS, A. Raychowdhury et al., Intel Corp.
-- Design Enablement in Scaled CMOS (Thursday afternoon), featuring:
- A 22nm Dynamically Adaptive Clock Distribution for Voltage Droop Tolerance, K. Bowman et al., Intel Corp.
- Voltage Droop Reduction Using Throttling Controlled by Timing Margin Feedback, M. Floyd et al., IBM Corp.
- An On-Die All-Digital Delay Measurement Circuit with 250fs Accuracy, M. Mansur et al., Intel Corp.
- A 47% Access Time Reduction with a Worst-Case Timing-Generation Scheme Utilizing a Statistical Method for Ultra Low Voltage SRAMs, A. Kawasumi et al., Toshiba
-- Embedded Memory (Thursday afternoon), featuring:
- Isolated Preset Architecture for a 32nm SOI embedded DRAM Macro, J. Barth et al., IBM Corp.
- A 260mV L-shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques, M.-P. Chen et al., National Tsing Hua University, ITRI, National Chung Hsing University, and Fukuoka Institute of Technology
- A 1.6-mm2 38-mW 1.5-Gb/s LDPC Decoder Enabled by Refresh-Free Embedded DRAM, Y.S. Park et al., University of Michigan
- 1Gsearch/sec Ternary Content Addressable Memory Compiler with Silicon-Aware Early-Predict Late-Correct Single-Ended Sensing, I. Arsovski et al., IBM Corp.
- A 2.8GHz 128-entry x 152b 3-Read/2-Write Multi-Precision Floating-Point Register File and Shuffler in 32nm CMOS, S. Hsu et al., Intel Corporation
Further Reading
