The big problem with extending down to smaller chip dimensions is that the features are smaller than the wavelength of the light used to for their lithography, leading to ragged edges and misshaped geometries that engineers have to fix with trial-and-error methods. The cool thing about directed self assembly is that you can use lithography at scales where the wavelength of light is not a problem, then depend on the self-assembling polymers to provide the super-small details with razor sharp edges and atomically perfect geometries: R. Colin Johnson
Here researchers demonstrate the contact hole layout for a 22-nm SRAM (top), using a guiding template created with conventional lithography (middle) resulting in the application of a block copolymer to self-assemble the circuit's contact pattern (bottom).
SOURCE: Stanford University
Here is what EETimes says about directed self assembly: A novel self-assembly technique previously demonstrated only in the lab for regular test patterns, has been perfected for creating the irregular patterns necessary to fabricate real semiconductors down to 14-nanometers, according to researchers funded by Semiconductor Research Corp. (SRC).
By solving one of the outstanding lithographic problems facing further scaling—the tiny contact holes that connect semiconductors to their substrate—researchers at Stanford University have demonstrated working circuits at 22-nanometer and a clear path to 14-nanometers, as well as a bee-line on the chemistry developments needed to scale to single digit sizes.