#CHIPS: "ISPD: Semiconductors aim for 8-nm node"

Microchips continue to scale down to smaller and smaller sizes, today measured in nanometers, with the current state-of-the-art 22 nanometer (for Intel) with the rest of the industry struggling to get to 32-nanometers. However, each year the future path to yet smaller microchip design rules is revealed at the IEEE International Symposium on Physical Design (ISPD) adn this year was no exception, with the roadmap for migration down to 8-nanometers unveiled by experts at Taiwan Semiconductor Manufacturing Company, Limited (TSMC), IBM and other industry leaders.


Mapper Lithography (Delft, the Netherlands) uses more than 10 thousand beamlets operating simultaneously as it aims for migration down to the 8-nanometer node.

The possible pathways down to the 8-nanometer semiconductor fabrication node were detailed last week at the ISPD (Napa, Calif.), albeit through a glass darkly. What's for sure is that the pathway is fraught with engineering peril as three competing technologies tool up for mass production capabilities. However, keynote speaker Burn Lin, a TSMC distinguished Fellow, claimed that one of three alternatives was sure to surmount the downward scaling hurdles to 8-nm design rules.

The three alternative pathways were 193-nanometer immersion lithography supplemented with multi-patterning, extreme ultraviolet (EUV) lithography and e-beam lithography. Immersion is closest to realization, according to Lin, but only if it can surmount spiraling cost barriers. EUV at the 13.5-nanometer wavelength has already been demonstrated capable of sub-20-nanometer design rules, but needs better focusing mechanisms and higher output light sources to overcome reflectivity of optics as low as 65 percent. E-beam is known to be able to achieve the 8-nanometer node today, but is a last-resort technology due to its slow speed and low throughput.
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