Wednesday, April 11, 2012

#CHIPS: "Internet-on-a-chip ties multi-cores"

Next month at DAC (June 3-7) MIT will hawk the Internet-on-a-Chip (IoaC) as the next-generation of on-chip interconnect for processors with 10-or more cores. Two cool techniques smooth the IoaC--"virtual bypassing" to maximally boost speed by sending a probe signal through on-chip routers to preset switches before a data burst, and tiny .3 volt switching to cut power by 38 percent.

Intel's 80-core experimental TeraFLOPS chip had an on-chip router to implement an Internet-on-a-chip, but never made it to production.

Here is what EETimes says about IoaC: On-chip busses and ring toplologies in use today will be more trouble than they are worth, making on-chip mesh networks the preferred architecture for massively parallel processors, according to according to researchers at the Massachusetts Institute of Technology (MIT).

Intel used an on-chip mesh network with integrated router for its experimental 80-core TeraFLOPs processor of a few years ago, but the most sophisticated on-chip network on any production processor is the ring-network on its latest eight-core XeonE5-2600. Dropping back to a ring topology, however, is just a stop-gap, according to Peh, who claims his recent study shows that at 16-cores or above, Intel, IBM, ARM, Freescale, Samsung and every other multi-core processor maker will have to go to an on-chip mesh network with integrated router.

Today nearly all multi-core processors use a conventional bus architecture which overlays a bus above the cores to connect them to each other and to memory, but the last stop for the bus will be above quad-cores, according to Peh, prompting some chip makers to go to dual busses and Intel to go to a ring network topology for its Xeon E5-2600. Above 16-cores, however, all manufactures will have to adopt the Internet-on-a-chip topology.
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