#CHIPS: "Ultra-Dense Microchips Going 3D"

The advanced semiconductor nodes are demanding that designers scrutinize the physical structures they propose before they actually fab them. Experienced designers depend on their personal knowledge bases, but as design rules shrink increasingly odd-ball discontinuities are popping up, especially at the boundaries of 3D structures like FinFETs. Tools exist for simulating detailed 3D structures, but usually only in very small areas, since they are incredibly computationally intensive. As a result, MEMS tools like this one which make estimations that the detailed tools won't allow are becoming more popular for "what if" scenarios that allow designers the luxury of making educated guesses, then confirming their suspicions before they fire up their conventional toolset.


SEMulator3D can model the micro-electro-mechanical structures on the most advanced semiconductors such as this FinFET SRAM cells with a high-K metal gate.

Here is what EETimes says about EDA tools:
Reaching the advanced semiconductor process nodes at 22-nanometer and beyond requires accurate three-dimensional (3-D) models of the proposed physical structures to obviate the need for repeated trial-and-error design cycles. In fact, the International Technology Roadmap for Semiconductors has designated modeling 3D physical structures as a "grand challenge" at advanced processing nodes.

One of the few tools capable of modeling the ultra-compact structures of FinFETs and other 3-D transistor structures is SEMulator3D, which was originally created by EDA software house Conventor Inc. (Cary, North Carolina) for MEMS designs, but which today is used almost exclusively for advanced semiconductor designs. IBM, for instance, has chosen SEMulator3D to design its FinFETs at the 22-nanometer node and beyond.

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