Here is what EETimes says about Silicon Labs new clock design service: Silicon Laboratories Inc. (NASDAQ: SLAB), a leader in high-performance, analog-intensive, mixed-signal ICs, today announced an online Clock Tree Design Service that gives customers quick access to Silicon Labs’ experienced applications engineering team to provide custom timing architecture proposals that simplify design, reduce BOM costs and minimize risk during development. When combined with the industry’s shortest component lead times of two weeks or less, Silicon Labs’ clock and oscillator family is designed to accelerate customers’ time to market. Performance-sensitive applications often require a combination of oscillators, clock generators and clock buffers to provide critical reference timing to high-speed SerDes devices, FPGAs, processors, data converters (ADC/DACs) and digital signal processors (DSPs). Not only is individual timing component selection critical, but system-level requirements also need to be taken into account to optimize performance. Silicon Labs’ online Clock Tree Design Service enables customers to enter their system-level timing requirements using a web-based utility, specifying multiple parameters including the number of clock inputs and outputs, input and output frequencies, signal formats and clock jitter. Silicon Labs’ applications engineering team reviews the requirements and provides a timing architecture optimized for performance, cost and lead time. Timing proposals are provided in just three business days, providing rapid feedback to customers...
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